With the increasing integration in information and communication technology, the requirements imposed on the constructing and connecting techniques are becoming ever greater. Ever higher requirements are imposed in particular on the package of the semiconductor chips. The package is the main medium for connecting the integrated circuit on the semiconductor chip to the rest of the system. A further reduction in the size of the structures on the semiconductor chip would be largely senseless if there were not a corresponding development in the packaging of the semiconductor chips.
To satisfy this high requirement on the packaging of the semiconductor chips, in recent years packaging methods for semiconductor chips have been proposed and developed under the designation “Chip Size Packaging” (CSP), in which the space requirement of the packaged semiconductor chip is not greater than approximately 1.2 times the unpackaged semiconductor chip. Accordingly, the integration density on the system board can be increased and parasitic effects of the package reduced, whereby ultimately the speed of the end product is significantly increased.
In the production of miniature housings for semiconductor chips, generally a specially preprocessed carrier substrate is used. This carrier substrate may in this case be designed such that it is both relatively flexible and relatively rigid_ Generally serving for attaching the semiconductor chip on the carrier substrate are full-area chip bonding tapes or elastomer layers, which in addition to fixing the semiconductor chip also serve for minimizing mechanical stresses of the overall arrangement. In particular, in the case of these technologies, the semiconductor chip is permanently connected to the carrier substrate by means of the double-sided adhesive chip bonding tapes or elastomer layers.
At the same time, packages of this type often have to satisfy extreme requirements with respect to stress absorption. In particular, it is necessary to compensate largely for thermally induced stresses, caused by different coefficients of expansion (CTE) of individual components of the package. In this respect it is generally attempted to reduce the thermomechanical stresses by means of the double-sided adhesive chip bonding tapes or elastomer layers, which to a certain extent have stress-absorbing properties. Unfortunately, so far there is no known method or material that satisfies this requirement satisfactorily. Therefore, instances of delamination in the package or damage to the semiconductor chip are repeatedly encountered.